A wide variety of design and computer-aided methods are utilized to implement state-of-the art electronic systems. Among the many tasks allotted to the design process and systems designers, few are more critical than decisions involving significant system and implementation tradeoffs during the design and layout processes. For example, overall system requirements can dictate balancing the system's performance, physical size, architectural complexity, power consumption, heat dissipation, fabrication complexity, cost, and other design criteria. Any one of such system and implementation tradeoffs made can cause profound impacts on the resulting system. The electronic systems in question can be implemented using a variety of techniques including custom-designed solutions (e.g. purpose-built circuits), or can be based on existing parts or libraries such as application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) and their variants, consumer off-the-shelf (COTS) components, or even microprocessors. Custom designed or ASIC-based systems are constructed to meet the most stringent systems requirements, and may consist of a variety of circuits and circuit types. While both custom and ASIC-based circuits do offer significant performance and size advantages, among other benefits, when compared to other circuit designs, they pose significant design and implementation challenges, including the placement of circuits and the wiring of power, ground, clock, and input/output signals.
Custom and ASIC-based systems contain many large, functional blocks of circuitry. These blocks, often referred to as macrocells, must be placed and connected with other blocks of circuitry comprising the rest of the integrated circuit system. These factors permit the reduction of design complexity, allow for circuit reuse, and provide a host of other benefits. These macrocells perform specific tasks, such as mathematical operations, and typically possess large numbers of active devices and input/output connections. Both the macrocells and their support wiring consume valuable real estate on the semiconductor chip. The macrocells and their many connections must be placed within and among other blocks of circuitry on the semiconductor chip. As with any circuit placement and routing, this placement of macrocells represents a complex design task, which is further complicated by many and often-competing system requirements. The placement cannot be arbitrarily performed, as the placement of macro cells must be balanced with system requirements, physical space availability, signal requirements, and other design criteria. The fact that macrocells are frequently clustered together logically—and often physically—on the semiconductor chip complicates the placement problem. This physical and logical clustering limits placement options for other required circuits and consumes valuable semiconductor chip real estate. Also, the placement of macrocells and other blocks of logic has a profound influence on system performance. Thus, many factors including timing must be considered while designing semiconductor chips.